LCD devices are widely used as display devices for use in TVs, graphic displays, and the like. Among these, attracting considerable attention are LCD devices in which each display pixel is equipped with a thin film transistor (hereinafter referred to as TFT) as a switching element, since such LCD devices produce display images which undergo no crosstalk between adjacent display pixels even in the case where display pixels therein increase in number.
Such an LCD device includes as main components an LCD panel 1 and a driving circuit section as shown in FIG. 9, and the LCD panel is formed by sealing liquid crystal composition between a pair of electrode substrates and applying deflecting plates onto outer surfaces of the electrode substrates.
A TFT array substrate which is one of the electrode substrates is formed by laying a plurality of signal lines S(1), S(2), . . . S(i), . . . S(N) and a plurality of scanning signal lines G(1), G(2), . . . G(j), . . . G(M) in a matrix form on a transparent insulating substrate 100 made of glass, for example. At each intersection of the signal lines and the scanning signal lines, a switching element 102 composed of a TFT which is connected with a pixel electrode 103 is formed, and an alignment film is provided so as to cover almost all of them. Thus, the TFT array substrate is formed.
On the other hand, a counter substrate which is the other electrode substrate is formed by laminating a counter electrode 101 and an alignment film all over a transparent insulating substrate made of, for example, glass, as the TFT array substrate. The driving circuit section is composed of a scanning signal line driving circuit 300, a signal line driving circuit 200, and a counter electrode driving circuit COM, which are connected with the scanning lines, the signal lines, and the counter electrode of the LCD panel thus formed, respectively. A control circuit 600 is a circuit for controlling both the signal line driving circuit 200 and the scanning signal line driving circuit 300.
The scanning signal line driving circuit (gate driver) 300 is composed of, for example, a shift register section 3a composed of M flip-flops cascaded, and selection switches 3b which are opened/closed in accordance with outputs of the flip-flops sent thereto, respectively, as shown in FIG. 10.
An input terminal VD1 out of two input terminals of each selection switch 3b is supplied with a gate-on voltage Vgh which is enough to cause the switching element 102 (see FIG. 9) to attain an ON state, while the other input terminal VD2 thereof is supplied with a gate-off voltage Vgl which is enough to cause the switching element 102 to attain an OFF state. Therefore, gate start signals (GSP) are sequentially transferred through the flip-flops in response to a clock signal (GCK) and are sequentially outputted to the selection switches 3b. In response to this, each selection switch 3b selects the voltage Vgh for turning on the TFT and outputs it to the scanning signal line 105 during one scanning period (TH), and thereafter outputs the voltage Vgl for turning off the TFT to the scanning signal line 105. With this operation, image signals outputted from the signal line driving circuit 200 to the respective signal lines 104 (see FIG. 9) can be written in respective corresponding pixels.
FIG. 11 illustrates an equivalent circuit of a one display pixel P(i, j) in which a pixel capacitor Clc and a supplementary capacitor Cs are connected in parallel to a counter potential VCOM of the counter electrode driving circuit COM. In the figure, Cgd represents a parasitic capacitance between a gate and a drain.
FIG. 12 illustrates driving waveforms of a conventional LCD device. In FIG. 12, Vg is a waveform of a signal for one scanning signal line, Vs is a waveform of a signal for one signal line, and Vd is a drain waveform.
Here, the following description will explain a conventional driving method, while referring to FIGS. 9, 11, and 12. Incidentally, it is widely known that liquid crystal requires alternating current drive so as to avoid occurrence of burn-in residual images and deterioration of displayed images, and the conventional driving method described below is explained by taking as an example a frame inversion drive which is a sort of the alternating current drive.
When a scanning voltage Vgh is applied from the scanning signal line driving circuit 300 to a gate electrode g(i, j) (see FIG. 9) of a TFT of one display pixel P(i, j) during a first field (TF1) as shown in FIG. 12, the TFT attains an ON state, and an image signal voltage Vsp from the signal line driving circuit 200 is applied to a pixel electrode through a source electrode and a drain electrode of the TFT. Until a scanning voltage Vgh is applied during the next field (TF2), the pixel electrode maintains a pixel potential Vdp as shown in FIG. 12. Since the counter electrode has a potential set to a predetermined counter potential VCOM by the counter electrode driving circuit COM, the liquid crystal composition held between the pixel electrode and the counter electrode responds in accordance with a potential difference between the pixel potential Vdp and the counter potential VCOM, whereby image display is carried out.
Likewise, when a scanning voltage Vgh is applied to a TFT gate electrode g(i, j) of one display pixel P(i, j) during the second field (TF2) from the scanning signal line driving circuit 300 as shown in FIG. 12, the TFT attains an ON state and an image signal voltage Vsn from the signal line driving circuit 200 is written in the pixel electrode. The pixel electrode maintains a pixel potential Vdn, and the liquid crystal composition responds in accordance with a potential difference between the pixel potential Vdn and the counter potential VCOM, whereby image display is carried out while liquid crystal alternating current drive is realized.
Since a parasitic capacitance Cgd is unavoidably formed between the gate and the drain of the TFT out of structural necessity as shown in FIG. 11, a level shift ΔVd caused by the parasitic capacitance Cgd occurs to the pixel potential Vd at a fall of the scanning voltage Vgh, as shown in FIG. 12. Let a non-scanning voltage (a voltage when the TFT is in the OFF state) of the scanning signal be Vgl, and the level shift ΔVd which thus occurs to the pixel potential Vd, caused by the parasitic capacitance Cgd which is unavoidably formed in the TFT, is expressed as:ΔVd=Cgd·(Vgh−Vgl)/(Clc+Cs+Cgd)Since the level shift causes a problem such as flickering of an image and deterioration of display, this is not favorable at all to LCD devices, of which higher definition and higher performance are required.
Therefore, conventionally has been proposed such a measure that the counter potential VCOM of the counter electrode is preliminarily biased so that the level shift ΔVd caused by the parasitic capacitance Cgd decreases.
By the foregoing conventional technique, however, it is difficult to arrange the scanning signal lines G(1), G(2), . . . G(j), . . . G(M) in such an ideal form that the scanning signal lines do not undergo signal delay transmission, and hence the scanning signal lines thus arranged results in constituting a signal delay path which undergoes signal delay to some extent.
FIG. 14 is a transmission equivalent circuit diagram in the case where signal transmission delay of one scanning signal line G(j) is focused. In FIG. 14, rg1, rg2, rg3, . . . rgN represent resistance components of wire materials forming the scanning signal lines and resistance components due to wire widths and wire lengths, mainly. cg1, cg2, cg3, . . . cgN represent various parasitic capacitances which are structurally capacitance-coupled with the scanning signal lines. The parasitic capacitances include cross capacitances which are generated at intersections of the scanning signal lines with the signal lines. Thus, the scanning signal lines constitute a signal delay transmission path of a distributed constant type.
FIG. 15 illustrates a state in which the scanning signal VG(j) supplied from the aforementioned scanning signal line driving circuit 300 to one scanning signal line dulls inside the panel due to the above-described signal delay transmission characteristic of the scanning signal line. In FIG. 15, a waveform Vg(1, j) is a waveform of the signal in the vicinity of a TFT gate electrode g(1, j) immediately after the output thereof from the scanning signal line driving circuit 300, and has substantially no dullness. In contrast, in the same figure, a waveform Vg(N, j) is a waveform of the signal in the vicinity of a TFT gate electrode g(N, j) at a farther end of the scanning signal line from the scanning signal line driving circuit 300, and has dulled due to the signal transmission delay characteristic of the scanning signal line. Due to the dullness, a shift takes place, whose change rate per unit time is indicated by SyN in the figure.
Further, the TFT is not perfectly an ON/OFF switch, but has a V-I characteristic (gate voltage-drain currency characteristic) as shown in FIG. 13. In FIG. 13, a voltage applied to the TFT gate is plotted as the axis of abscissa, while a drain voltage is plotted as the axis of ordinate. Normally the scanning pulse is composed of two voltage levels, one being a voltage level Vgh which is enough to cause the TFT to attain an ON state, while the other being a voltage level Vgl which is enough to cause the TFT to attain an OFF state. There however also exists an intermediate ON region (linear region) between a threshold level VT of the TFT and the level Vgh as shown in the figure.
Since the scanning signal therefore has a sharp fall from the level Vgh to the level Vgl at a pixel having the gate electrode g(1, j), immediately behind the output side of the scanning signal line driving circuit 300 as shown in FIG. 15, the characteristic in the linear region of the TFT does not influence the scanning signal there. As a result, the level shift ΔVd(1) which occurs to the pixel potential Vd(1, j) due to the parasitic capacitance Cgd can be approximated as follows:ΔVd(1)=Cgd·(Vgh−Vgl)/(Clc+Cs+Cgd)
On the other hand, at the pixel having the TFT gate electrode g(N, j) located in the vicinity of the farther end of the scanning signal line, the scanning signal has a dull fall. The characteristic of the linear region of the TFT therefore reversely affects, and this results in the following: the level shift which is to occur to the pixel potential Vd due to the parasitic capacitance Cgd does not occur during the fall of the scanning signal from the level Vgh to the TFT threshold level VT since the TFT maintains the intermediate ON state due to the linear state, whereas a level shift ΔVd(N) which is to occur to the pixel potential Vd(N, j) due to the parasitic capacitance Cgd occurs in a region in which the scanning signal further falls from the vicinity of the threshold level VT to the level Vgl. Therefore, the level shift ΔVd(N) becomes as follows:ΔVd(N)<Cgd·(Vgh−Vgl)/(Clc+Cs+Cgd)Thus, ΔVd(1)>ΔVd(N) is satisfied.
As described above, the level shifts ΔVd occurring to the pixel potentials Vd due to the parasitic capacitances Cgd inside the panel is not uniform throughout the display plane, and it becomes more hardly negligible as the LCD device has a larger screen and becomes higher-definition. Accordingly the conventional scheme of biasing the counter voltage becomes incapable of absorbing differences in the level shifts throughout the display plane, thereby being incapable of conducting optimal alternating current drive with respect to each pixel. Consequently defects such as flickering and burn-in residual images due to DC component application are induced (see the Japanese Publication for Laid-Open Patent Application No. 120720/1995 (Tokukaihei 7-120720, date of publication: May 12, 1995)).